In high-speed electrical links, spread spectrum clocking (SSC) may be employed to reduce electromagnetic interference. Spread spectrum clocking may, for example, modulate the clock frequency with a triangular waveform, e.g., apply a triangle wave frequency modulation to the clock signal. The frequency ramp corresponding to a half cycle of the triangle wave may result in a phase error that is approximately constant if a second order phase-locked loop (PLL) is employed to track the clock signal. This phase error may reduce timing margins in the system.
Dual loop semi-digital phase-locked loops, which may be employed to reduce this phase error, may have various drawbacks. Such a phase locked loop may employ additional phase interpolators, digital to analog converters, and adaptation loops to estimate the frequency ramp rate and transition points of the triangle wave. Using dual loop semi-digital phase-locked loops may also be quite costly in terms of power; especially in double data rate or quad data rate systems which employ multiple phases of clock.
Thus, there is a need for an improved system and method for locking to a frequency modulated reference clock signal.